Onur Mutlu - Major Publications#


1. Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, and Onur Mutlu, "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors", Proceedings of the 41st International Symposium on Computer Architecture (ISCA), Minneapolis, MN, June 2014.

First scientific work that discovered a failure mechanism called RowHammer in modern DRAM chips, which leads to system-wide security vulnerabilities. Makes the first practical, exploitable connection between hardware reliability and systems security. Heavily cited in systems, security, software, hardware communities and the media, and influenced processor and memory products.

2. Yu Cai, Erich F. Haratsch, Onur Mutlu, and Ken Mai, "Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis" Proceedings of the Design, Automation, and Test in Europe Conference (DATE), Dresden, Germany, March 2012.

First scientific work providing real experimental error data on modern flash memory chips. Used for educating engineers in most flash memory companies, including Samsung, SK Hynix, Seagate, Sandisk, Micron, Toshiba.

3. Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger, "Architecting Phase Change Memory as a Scalable DRAM Alternative" Proceedings of the 36th International Symposium on Computer Architecture (ISCA), Austin, TX, June 2009.

One of the 13 computer architecture papers of 2009 selected as Top Picks by IEEE Micro. Selected as a CACM Research Highlight.-

First scientific work to advocate and analyze the use of non-volatile Phase Change Memory technologies in main memory. Precursor of modern 3D XPoint from Intel and other non-volatile memory technologies that are being designed for main memory.

4. Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt, "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors" Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA), Anaheim, CA, February 2003.

One of the 15 computer architecture papers of 2003 selected as Top Picks by IEEE Micro.

Variants of runahead execution proposed in this work is implemented in cutting-edge IBM and Sun Microsystems processors.

5. Onur Mutlu and Thomas Moscibroda, "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems" Proceedings of the 35th International Symposium on Computer Architecture (ISCA), Beijing, China, June 2008.

One of the 12 computer architecture papers of 2008 selected as Top Picks by IEEE Micro.

The paper, together with the one below, opened up significant research into memory controllers in academia and industry. Variant of the proposed method is implemented in Samsung memory controllers.

6. Onur Mutlu and Thomas Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors" Proceedings of the 40th International Symposium on Microarchitecture (MICRO), Chicago, IL, December 2007.

The paper, together with the one above, opened up significant research into memory controllers in academia and industry.

7. Jamie Liu, Ben Jaiyen, Richard Veras, and Onur Mutlu, "RAIDR: Retention-Aware Intelligent DRAM Refresh" Proceedings of the 39th International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012.

The paper opened up significant architectural research into the DRAM refresh problem. Opening paper of the conference.

8. Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, and Onur Mutlu, "An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms" Proceedings of the 40th International Symposium on Computer Architecture (ISCA), Tel-Aviv, Israel, June 2013.

The paper, along with the one right above, opened up significant architectural research into the DRAM refresh problem.

9. Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, and Onur Mutlu, "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM" Proceedings of the 39th International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012.

One of the pioneering architectural works in enhancing DRAM scaling. The proposed method is being advocated for use in the next-generation DRAM standards by Samsung and Intel.

10. Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, "A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing" Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), Portland, OR, June 2015.

One of the first complete system designs for taking advantage of processing in memory with 3D-stacked technologies. The paper led to a flurry of recent research in system and application design to take advantage of processing in memory with 3D-stacked technologies.

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