Georges Gielen - Selected Publications#

[March 2018] Google Scholar records: h=55, i10=258 -- 55 PhD students graduated - 182 peer-reviewed journal papers

A. Expert in computer-aided design (CAD) and design automation of analog and mixed-signal integrated circuits
Publications [the overview papers in the Proceedings of the IEEE are highly cited references in the field]

1) B. Liu, Q. Zhang, G. Gielen, "A Gaussian process surrogate model assisted evolutionary algorithm for medium scale expensive optimization problems," IEEE Transactions on Evolutionary Computation, Vol. 18, No. 2, pp. 180-192, 2014.

2) R. Rutenbar, G. Gielen, J. Roychowdhury, “Hierarchical modeling, optimization and synthesis for system-level analog and RF design,” Proceedings of the IEEE, Vol. 95, No. 3, pp. 640-669, 2007.

3) G. Gielen, R. Rutenbar, “Computer-aided design of analog and mixed-signal integrated circuits,” Proceedings of the IEEE, Vol. 88, No. 12, pp. 1825-1854, 2000.

4) G. Gielen, H. Walscharts, W. Sansen, "ISAAC: a symbolic simulator for analog integrated circuits," IEEE Journal of Solid-State Circuits, Vol. 24, No. 6, pp. 1587-1597, 1989.
Motivation : The candidate has made significant contributions as researcher and leader of a team of PhD students to the field of computer-aided design (CAD) and design automation of analog and mixed-signal integrated circuits and systems. He has built up expertise towards effective and efficient algorithms for the analysis and optimized design of analog circuits and systems, including research on symbolic analysis and performance modeling of analog circuits, the analysis of the impact of variability, substrate noise or device aging on circuit performance, the automated design, optimization and synthesis of integrated circuits, etc. Significant breakthrough contributions in this area have been made, by developing novel methods and algorithms, demonstrating them in prototype software tool implementations and applying them to top-class fabricated and measured designs. Very famous is the research on the symbolic simulator ISAAC.

B. Innovative circuit design techniques based on solid understanding of performance limitations

5) G. Gielen et al, “Time-based sensor interface circuits in CMOS and carbon nanotube technologies,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 63, No. 5, pp. 577-586, 2016.

6) C. Lopez, …., G. Gielen, “An implantable 455-active-electrode 52-channel CMOS neural probe,” IEEE Journal of Solid-State Circuits, Vol. 49, No. 1, pp. 248-261, 2014.

7) G. Van der Plas, J. Vandenbussche, W. Sansen, M. Steyaert, G. Gielen, “A 14-bit intrinsic accuracy Q^2 random walk CMOS DAC,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 12, pp. 1708-1718, 1999.
Motivation : The design research of the candidate is characterized by a thorough exploration of the fundamental barriers and limitations to the performance of the targeted circuits, be it functional (e.g. power, noise) or parametric (e.g. impact of mismatch/tolerances, aging phenomena, etc.). Based on this understanding, research is then carried out to develop innovative circuit solutions that push the state of the art, e.g. low-power time-based sensor interfaces, digitally-assisted analog circuits, aging-robust self-healing analog circuits, high-performance data converters, etc. Three well-referenced example papers are given.

C. Novel structural testing and design for testability of analog/mixed-signal circuits

8) A. Coyette, B. Esen, N. Xama, W. Dobbelaere, R. Vanhooren, G. Gielen, "ADAGE: automated DfT-assisted generation of test stimuli for mixed-signal integrated circuits," IEEE Design & Test, 2018.

9) G. Gielen, et al., “Design and test of analog circuits towards sub-ppm level,” proc. International Test Conference (ITC), 2014 (invited keynote)
Georges Gielen has built up innovative research to develop a defect-oriented structural test design approach for analog circuits that quantifies the defect coverage through fault modeling and simulation. This includes research on design for testability techniques and on automated test signal generation algorithms that have effectively brought the test escape rate down from several 100 ppm to sub-ppm quality levels in industrial automotive ICs.

D. Georges Gielen has published as author or co-author 10 books (plus 3 books as editor), including as an example:

10) E. Maricau, G. Gielen, "Analog IC reliability in nanometer CMOS," Springer, 2013.

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