!!Manolis Katevenis - Selected Publications
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List of the major works (especially recent ones) that have been responsible for the international recognition of  Katevenis:\\
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(Citations: According to "Harzing Publish or Perish v.3.0.3813", run on 10 May 2012, with Query: "Katevenis from 1970 to 2012: all": Papers: 140; Citations: 2038; h-index: 23.  )\\
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__RISC Architectures:__\\
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*M. Katevenis: ''Reduced Instruction Set Computer Architectures for VLSI'', 1984 ACM Doctoral Dissertation Award, MIT Press, ISBN 0-262-11103-9, 1985 (290 citations to this and its earlier Technical Report version).\\
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__Interconnection Network and Packet Switch Architectures:__\\
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*M. Katevenis: ''Fast Switching and Fair Control of Congested Flow in Broad-Band Networks'', IEEE Journal on Selected Areas in Communications (JSAC), vol. 5, no. 8, pp. 1315-1326, October 1987 (100 citations).\\
*Katevenis, Sidiropoulos, Courcoubetis: ''Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip'', IEEE Journal on Selected Areas in Communications (JSAC), vol. 9, no. 8, pp. 1265-1279, October 1991 (440 citations).\\
*M. Katevenis, P. Vatsolaki, A. Efthymiou: ''Pipelined Memory Shared Buffer for VLSI Switches'', Proc. of the ACM SIGCOMM '95 Conference, Cambridge, MA USA, 30 August - 1 Sep. 1995, pp. 39-48 (80 citations).\\
*M. Katevenis, D. Serpanos, E. Spyridakis: ''Credit-Flow-Controlled ATM for MP Interconnection: the ATLAS I Single-Chip ATM Switch'', Proc. of the 4th IEEE Int. Symp. on High-Performance Computer Architecture (HPCA 1998), Las Vegas, NV USA, Feb. 1998, pp. 47-56 (ATLAS I chip papers: 126 total citations: HotI'96 (43), ARVLSI'97 (29), Globecom'97 (25), HPCA'98 (29)).\\
*Ioannou, Katevenis: ''Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High Speed Networks'', IEEE/ACM Transactions on Networking (ToN), vol. 15, no. 2, pp. 450-461, Apr. 2007 (40 citations to this & prev. ICC'01 paper).\\
*N. Chrysos, M. Katevenis: ''Distributed WFQ scheduling converging to weighted max-min fairness'', Computer Networks (Elsevier), vol. 55, issue 3, Oct. 2010 (on-line), Feb. 2011 (in print), pp. 792-806.\\
*G. Passas, M. Katevenis, D. Pnevmatikatos: ''Crossbar NoCs Are Scalable Beyond 100 Nodes'', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, issue 4, April 2012, pp. 573-585.\\
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__Interprocessor Communication for Scalable Parallelism:__\\
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*E. Markatos, M. Katevenis: ''Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters'', Proc. IEEE Int. Symp. High-Perf. Comp. Arch. (HPCA 1996), San Jose USA, Feb. 1996, pp.144-153 (68 citations to this and prev. TR).\\
*E. Markatos, M. Katevenis: ''User-Level DMA without Operating System Kernel Modification'', Proc. 3rd IEEE Int. Symp. on High-Performance Computer Architecture (HPCA 1997), San Antonio, TX USA, Feb. 1997, pp. 322-331 (32 citations).\\
*M. Katevenis, V. Papaefstathiou, S. Kavadias, D. Pnevmatikatos, F. Silla, D. Nikolopoulos: ''Explicit Communication and Synchronization in SARC'', IEEE Micro, vol. 30, no. 5, pp. 30-41, September/October 2010.